1. Field of the Invention
The present invention relates generally to a method for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The subject invention biases the composition of the integrated circuit chip scan paths to allow them to also function as on-product process monitors, and adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases inter-cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The grouping of structures with similar process sensitivities into a scan chain allows scan chain fails during test to be more easily correlated back to a subset of fabrication process steps and related root causes.
2. Discussion of the Prior Art
The semiconductor industry places a premium on the ability of new technologies to increase yields of semiconductor chips. Test and yield-enhancing methodologies that improve the yield of semiconductor chips are highly prized. One such methodology for yield characterization is the analysis of scan chain yield on specific chip products.
The present state of the art of designing scan chains is based primarily upon spatial considerations and scan chain length (e.g. 10,000 latches in a scan chain), which is the number of latches in a scan chain. In the current state of the art, scan chain design is not systematically coupled with fabrication process sensitivities. On occasion, a systematic failure of a scan chain design has been discovered to be dominated by a particular fabrication process feature or level, which provided insight into a systematic problem in the fabrication process. In the current state of the art, scan chain sensitivity to a specific process level is neither planned nor understood prior to test, but rather results from a post production analysis of yield data and scan chain design for a particular chip design.